Static Timing Analysis

Project : eS-WiFi_Client_Server
Build Time : 11/15/16 15:09:11
Device : CY8C4248BZI-L489
Temperature : -40C - 85C
VBUS : 5.00
VDDA_0 : 3.30
VDDA_1 : 3.30
VDDA_CTB : 3.30
VDDD : 3.30
VDDIO : 3.30
VDDIO_0 : 3.30
VDDIO_1 : 3.30
VDDIO_2 : 3.30
VDDIO_3 : 3.30
VDDIO_4 : 3.30
VDDIO_A : 3.30
VDDIO_A_1 : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
Clock_PWM(FFB) Clock_PWM(FFB) 48.000 MHz 48.000 MHz N/A
CyHFCLK CyHFCLK 48.000 MHz 48.000 MHz 50.166 MHz
Clock_PWM CyHFCLK 48.000 MHz 48.000 MHz N/A
UART_ESWIFI_IntClock CyHFCLK 923.077 kHz 923.077 kHz 43.516 MHz
UART_DBG_SCBCLK CyHFCLK 1.371 MHz 1.371 MHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 48.000 MHz 48.000 MHz N/A
CyLFCLK CyLFCLK 32.000 kHz 32.000 kHz N/A
CyRouted1 CyRouted1 48.000 MHz 48.000 MHz N/A
CySYSCLK CySYSCLK 48.000 MHz 48.000 MHz N/A
UART_DBG_SCBCLK(FFB) UART_DBG_SCBCLK(FFB) 1.371 MHz 1.371 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 20.8333ns(48 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer:TimerUDB:sT8:timerdp:u0\/cs_addr_1 55.313 MHz 18.079 2.754
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,3) 1 \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \Timer:TimerUDB:control_7\ \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer:TimerUDB:sT8:timerdp:u0\/cs_addr_1 3.979
datapathcell4 U(1,1) 1 \Timer:TimerUDB:sT8:timerdp:u0\ SETUP 11.520
Clock Skew 0.000
\Timer:TimerUDB:sT8:timerdp:u0\/z0_comb \Timer:TimerUDB:sT8:timerdp:u0\/cs_addr_0 55.642 MHz 17.972 2.861
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(1,1) 1 \Timer:TimerUDB:sT8:timerdp:u0\ \Timer:TimerUDB:sT8:timerdp:u0\/clock \Timer:TimerUDB:sT8:timerdp:u0\/z0_comb 3.850
datapathcell4 U(1,1) 1 \Timer:TimerUDB:sT8:timerdp:u0\ \Timer:TimerUDB:sT8:timerdp:u0\/z0_comb \Timer:TimerUDB:sT8:timerdp:u0\/cs_addr_0 2.602
datapathcell4 U(1,1) 1 \Timer:TimerUDB:sT8:timerdp:u0\ SETUP 11.520
Clock Skew 0.000
\Timer:TimerUDB:sT8:timerdp:u0\/z0_comb \Timer:TimerUDB:rstSts:stsreg\/status_0 65.837 MHz 15.189 5.644
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(1,1) 1 \Timer:TimerUDB:sT8:timerdp:u0\ \Timer:TimerUDB:sT8:timerdp:u0\/clock \Timer:TimerUDB:sT8:timerdp:u0\/z0_comb 3.850
Route 1 \Timer:TimerUDB:per_zero\ \Timer:TimerUDB:sT8:timerdp:u0\/z0_comb \Timer:TimerUDB:status_tc\/main_1 4.108
macrocell9 U(1,3) 1 \Timer:TimerUDB:status_tc\ \Timer:TimerUDB:status_tc\/main_1 \Timer:TimerUDB:status_tc\/q 3.350
Route 1 \Timer:TimerUDB:status_tc\ \Timer:TimerUDB:status_tc\/q \Timer:TimerUDB:rstSts:stsreg\/status_0 2.311
statusicell3 U(1,3) 1 \Timer:TimerUDB:rstSts:stsreg\ SETUP 1.570
Clock Skew 0.000
\Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer:TimerUDB:rstSts:stsreg\/status_0 82.413 MHz 12.134 8.699
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,3) 1 \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \Timer:TimerUDB:control_7\ \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer:TimerUDB:status_tc\/main_0 2.323
macrocell9 U(1,3) 1 \Timer:TimerUDB:status_tc\ \Timer:TimerUDB:status_tc\/main_0 \Timer:TimerUDB:status_tc\/q 3.350
Route 1 \Timer:TimerUDB:status_tc\ \Timer:TimerUDB:status_tc\/q \Timer:TimerUDB:rstSts:stsreg\/status_0 2.311
statusicell3 U(1,3) 1 \Timer:TimerUDB:rstSts:stsreg\ SETUP 1.570
Clock Skew 0.000
Path Delay Requirement : 20.8333ns(48 MHz)
Affects clock : CyHFCLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)/fb \UART_ESWIFI:BUART:sRX:RxShifter:u0\/route_si 50.166 MHz 19.934 0.899
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P1[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_620 Rx_1(0)/fb \UART_ESWIFI:BUART:rx_postpoll\/main_1 5.038
macrocell6 U(1,2) 1 \UART_ESWIFI:BUART:rx_postpoll\ \UART_ESWIFI:BUART:rx_postpoll\/main_1 \UART_ESWIFI:BUART:rx_postpoll\/q 3.350
Route 1 \UART_ESWIFI:BUART:rx_postpoll\ \UART_ESWIFI:BUART:rx_postpoll\/q \UART_ESWIFI:BUART:sRX:RxShifter:u0\/route_si 2.289
datapathcell3 U(1,2) 1 \UART_ESWIFI:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
Rx_1(0)/fb \UART_ESWIFI:BUART:rx_state_0\/main_9 73.877 MHz 13.536 7.297
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P1[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_620 Rx_1(0)/fb \UART_ESWIFI:BUART:rx_state_0\/main_9 5.979
macrocell16 U(1,1) 1 \UART_ESWIFI:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_ESWIFI:BUART:rx_state_2\/main_8 73.948 MHz 13.523 7.310
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P1[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_620 Rx_1(0)/fb \UART_ESWIFI:BUART:rx_state_2\/main_8 5.966
macrocell19 U(1,1) 1 \UART_ESWIFI:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_ESWIFI:BUART:rx_status_3\/main_6 73.948 MHz 13.523 7.310
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P1[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_620 Rx_1(0)/fb \UART_ESWIFI:BUART:rx_status_3\/main_6 5.966
macrocell24 U(1,1) 1 \UART_ESWIFI:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_ESWIFI:BUART:pollcount_1\/main_3 74.761 MHz 13.376 7.457
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P1[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_620 Rx_1(0)/fb \UART_ESWIFI:BUART:pollcount_1\/main_3 5.819
macrocell22 U(1,3) 1 \UART_ESWIFI:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_ESWIFI:BUART:pollcount_0\/main_2 79.397 MHz 12.595 8.238
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P1[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_620 Rx_1(0)/fb \UART_ESWIFI:BUART:pollcount_0\/main_2 5.038
macrocell23 U(1,2) 1 \UART_ESWIFI:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_ESWIFI:BUART:rx_last\/main_0 79.397 MHz 12.595 8.238
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P1[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_620 Rx_1(0)/fb \UART_ESWIFI:BUART:rx_last\/main_0 5.038
macrocell25 U(1,2) 1 \UART_ESWIFI:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 1083.33ns(923.077 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_ESWIFI:BUART:tx_state_1\/q \UART_ESWIFI:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 43.516 MHz 22.980 1060.353
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(0,3) 1 \UART_ESWIFI:BUART:tx_state_1\ \UART_ESWIFI:BUART:tx_state_1\/clock_0 \UART_ESWIFI:BUART:tx_state_1\/q 1.250
Route 1 \UART_ESWIFI:BUART:tx_state_1\ \UART_ESWIFI:BUART:tx_state_1\/q \UART_ESWIFI:BUART:counter_load_not\/main_0 4.560
macrocell2 U(0,2) 1 \UART_ESWIFI:BUART:counter_load_not\ \UART_ESWIFI:BUART:counter_load_not\/main_0 \UART_ESWIFI:BUART:counter_load_not\/q 3.350
Route 1 \UART_ESWIFI:BUART:counter_load_not\ \UART_ESWIFI:BUART:counter_load_not\/q \UART_ESWIFI:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.300
datapathcell2 U(0,2) 1 \UART_ESWIFI:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_ESWIFI:BUART:tx_state_0\/q \UART_ESWIFI:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 44.689 MHz 22.377 1060.956
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(0,3) 1 \UART_ESWIFI:BUART:tx_state_0\ \UART_ESWIFI:BUART:tx_state_0\/clock_0 \UART_ESWIFI:BUART:tx_state_0\/q 1.250
Route 1 \UART_ESWIFI:BUART:tx_state_0\ \UART_ESWIFI:BUART:tx_state_0\/q \UART_ESWIFI:BUART:counter_load_not\/main_1 3.957
macrocell2 U(0,2) 1 \UART_ESWIFI:BUART:counter_load_not\ \UART_ESWIFI:BUART:counter_load_not\/main_1 \UART_ESWIFI:BUART:counter_load_not\/q 3.350
Route 1 \UART_ESWIFI:BUART:counter_load_not\ \UART_ESWIFI:BUART:counter_load_not\/q \UART_ESWIFI:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.300
datapathcell2 U(0,2) 1 \UART_ESWIFI:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_ESWIFI:BUART:tx_state_2\/q \UART_ESWIFI:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.447 MHz 21.530 1061.803
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(0,2) 1 \UART_ESWIFI:BUART:tx_state_2\ \UART_ESWIFI:BUART:tx_state_2\/clock_0 \UART_ESWIFI:BUART:tx_state_2\/q 1.250
Route 1 \UART_ESWIFI:BUART:tx_state_2\ \UART_ESWIFI:BUART:tx_state_2\/q \UART_ESWIFI:BUART:counter_load_not\/main_3 3.110
macrocell2 U(0,2) 1 \UART_ESWIFI:BUART:counter_load_not\ \UART_ESWIFI:BUART:counter_load_not\/main_3 \UART_ESWIFI:BUART:counter_load_not\/q 3.350
Route 1 \UART_ESWIFI:BUART:counter_load_not\ \UART_ESWIFI:BUART:counter_load_not\/q \UART_ESWIFI:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.300
datapathcell2 U(0,2) 1 \UART_ESWIFI:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_ESWIFI:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_ESWIFI:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 47.749 MHz 20.943 1062.390
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,2) 1 \UART_ESWIFI:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_ESWIFI:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_ESWIFI:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 1.000
Route 1 \UART_ESWIFI:BUART:tx_bitclk_enable_pre\ \UART_ESWIFI:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_ESWIFI:BUART:counter_load_not\/main_2 2.773
macrocell2 U(0,2) 1 \UART_ESWIFI:BUART:counter_load_not\ \UART_ESWIFI:BUART:counter_load_not\/main_2 \UART_ESWIFI:BUART:counter_load_not\/q 3.350
Route 1 \UART_ESWIFI:BUART:counter_load_not\ \UART_ESWIFI:BUART:counter_load_not\/q \UART_ESWIFI:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.300
datapathcell2 U(0,2) 1 \UART_ESWIFI:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_ESWIFI:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_ESWIFI:BUART:sTX:TxSts\/status_0 50.213 MHz 19.915 1063.418
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,3) 1 \UART_ESWIFI:BUART:sTX:TxShifter:u0\ \UART_ESWIFI:BUART:sTX:TxShifter:u0\/clock \UART_ESWIFI:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART_ESWIFI:BUART:tx_fifo_empty\ \UART_ESWIFI:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_ESWIFI:BUART:tx_status_0\/main_3 3.883
macrocell3 U(0,3) 1 \UART_ESWIFI:BUART:tx_status_0\ \UART_ESWIFI:BUART:tx_status_0\/main_3 \UART_ESWIFI:BUART:tx_status_0\/q 3.350
Route 1 \UART_ESWIFI:BUART:tx_status_0\ \UART_ESWIFI:BUART:tx_status_0\/q \UART_ESWIFI:BUART:sTX:TxSts\/status_0 5.832
statusicell1 U(0,2) 1 \UART_ESWIFI:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\UART_ESWIFI:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART_ESWIFI:BUART:sRX:RxSts\/status_4 56.693 MHz 17.639 1065.694
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(1,2) 1 \UART_ESWIFI:BUART:sRX:RxShifter:u0\ \UART_ESWIFI:BUART:sRX:RxShifter:u0\/clock \UART_ESWIFI:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART_ESWIFI:BUART:rx_fifofull\ \UART_ESWIFI:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART_ESWIFI:BUART:rx_status_4\/main_1 2.919
macrocell7 U(0,1) 1 \UART_ESWIFI:BUART:rx_status_4\ \UART_ESWIFI:BUART:rx_status_4\/main_1 \UART_ESWIFI:BUART:rx_status_4\/q 3.350
Route 1 \UART_ESWIFI:BUART:rx_status_4\ \UART_ESWIFI:BUART:rx_status_4\/q \UART_ESWIFI:BUART:sRX:RxSts\/status_4 4.520
statusicell2 U(1,2) 1 \UART_ESWIFI:BUART:sRX:RxSts\ SETUP 1.570
Clock Skew 0.000
\UART_ESWIFI:BUART:tx_state_2\/q \UART_ESWIFI:BUART:sTX:TxSts\/status_0 59.365 MHz 16.845 1066.488
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(0,2) 1 \UART_ESWIFI:BUART:tx_state_2\ \UART_ESWIFI:BUART:tx_state_2\/clock_0 \UART_ESWIFI:BUART:tx_state_2\/q 1.250
Route 1 \UART_ESWIFI:BUART:tx_state_2\ \UART_ESWIFI:BUART:tx_state_2\/q \UART_ESWIFI:BUART:tx_status_0\/main_4 4.843
macrocell3 U(0,3) 1 \UART_ESWIFI:BUART:tx_status_0\ \UART_ESWIFI:BUART:tx_status_0\/main_4 \UART_ESWIFI:BUART:tx_status_0\/q 3.350
Route 1 \UART_ESWIFI:BUART:tx_status_0\ \UART_ESWIFI:BUART:tx_status_0\/q \UART_ESWIFI:BUART:sTX:TxSts\/status_0 5.832
statusicell1 U(0,2) 1 \UART_ESWIFI:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\UART_ESWIFI:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_ESWIFI:BUART:sTX:TxSts\/status_0 61.151 MHz 16.353 1066.980
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,2) 1 \UART_ESWIFI:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_ESWIFI:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_ESWIFI:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 1.000
Route 1 \UART_ESWIFI:BUART:tx_bitclk_enable_pre\ \UART_ESWIFI:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_ESWIFI:BUART:tx_status_0\/main_2 4.601
macrocell3 U(0,3) 1 \UART_ESWIFI:BUART:tx_status_0\ \UART_ESWIFI:BUART:tx_status_0\/main_2 \UART_ESWIFI:BUART:tx_status_0\/q 3.350
Route 1 \UART_ESWIFI:BUART:tx_status_0\ \UART_ESWIFI:BUART:tx_status_0\/q \UART_ESWIFI:BUART:sTX:TxSts\/status_0 5.832
statusicell1 U(0,2) 1 \UART_ESWIFI:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\UART_ESWIFI:BUART:tx_state_1\/q \UART_ESWIFI:BUART:sTX:TxSts\/status_0 62.858 MHz 15.909 1067.424
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(0,3) 1 \UART_ESWIFI:BUART:tx_state_1\ \UART_ESWIFI:BUART:tx_state_1\/clock_0 \UART_ESWIFI:BUART:tx_state_1\/q 1.250
Route 1 \UART_ESWIFI:BUART:tx_state_1\ \UART_ESWIFI:BUART:tx_state_1\/q \UART_ESWIFI:BUART:tx_status_0\/main_0 3.907
macrocell3 U(0,3) 1 \UART_ESWIFI:BUART:tx_status_0\ \UART_ESWIFI:BUART:tx_status_0\/main_0 \UART_ESWIFI:BUART:tx_status_0\/q 3.350
Route 1 \UART_ESWIFI:BUART:tx_status_0\ \UART_ESWIFI:BUART:tx_status_0\/q \UART_ESWIFI:BUART:sTX:TxSts\/status_0 5.832
statusicell1 U(0,2) 1 \UART_ESWIFI:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\UART_ESWIFI:BUART:tx_ctrl_mark_last\/q \UART_ESWIFI:BUART:sRX:RxBitCounter\/load 63.715 MHz 15.695 1067.638
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(1,1) 1 \UART_ESWIFI:BUART:tx_ctrl_mark_last\ \UART_ESWIFI:BUART:tx_ctrl_mark_last\/clock_0 \UART_ESWIFI:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART_ESWIFI:BUART:tx_ctrl_mark_last\ \UART_ESWIFI:BUART:tx_ctrl_mark_last\/q \UART_ESWIFI:BUART:rx_counter_load\/main_0 4.560
macrocell5 U(1,1) 1 \UART_ESWIFI:BUART:rx_counter_load\ \UART_ESWIFI:BUART:rx_counter_load\/main_0 \UART_ESWIFI:BUART:rx_counter_load\/q 3.350
Route 1 \UART_ESWIFI:BUART:rx_counter_load\ \UART_ESWIFI:BUART:rx_counter_load\/q \UART_ESWIFI:BUART:sRX:RxBitCounter\/load 2.315
count7cell U(1,1) 1 \UART_ESWIFI:BUART:sRX:RxBitCounter\ SETUP 4.220
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\Timer:TimerUDB:sT8:timerdp:u0\/z0_comb \Timer:TimerUDB:sT8:timerdp:u0\/cs_addr_0 5.872
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(1,1) 1 \Timer:TimerUDB:sT8:timerdp:u0\ \Timer:TimerUDB:sT8:timerdp:u0\/clock \Timer:TimerUDB:sT8:timerdp:u0\/z0_comb 3.270
datapathcell4 U(1,1) 1 \Timer:TimerUDB:sT8:timerdp:u0\ \Timer:TimerUDB:sT8:timerdp:u0\/z0_comb \Timer:TimerUDB:sT8:timerdp:u0\/cs_addr_0 2.602
datapathcell4 U(1,1) 1 \Timer:TimerUDB:sT8:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
\Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer:TimerUDB:sT8:timerdp:u0\/cs_addr_1 6.019
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,3) 1 \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.040
Route 1 \Timer:TimerUDB:control_7\ \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer:TimerUDB:sT8:timerdp:u0\/cs_addr_1 3.979
datapathcell4 U(1,1) 1 \Timer:TimerUDB:sT8:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
\Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer:TimerUDB:rstSts:stsreg\/status_0 8.024
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,3) 1 \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.040
Route 1 \Timer:TimerUDB:control_7\ \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer:TimerUDB:status_tc\/main_0 2.323
macrocell9 U(1,3) 1 \Timer:TimerUDB:status_tc\ \Timer:TimerUDB:status_tc\/main_0 \Timer:TimerUDB:status_tc\/q 3.350
Route 1 \Timer:TimerUDB:status_tc\ \Timer:TimerUDB:status_tc\/q \Timer:TimerUDB:rstSts:stsreg\/status_0 2.311
statusicell3 U(1,3) 1 \Timer:TimerUDB:rstSts:stsreg\ HOLD -2.000
Clock Skew 0.000
\Timer:TimerUDB:sT8:timerdp:u0\/z0_comb \Timer:TimerUDB:rstSts:stsreg\/status_0 11.039
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(1,1) 1 \Timer:TimerUDB:sT8:timerdp:u0\ \Timer:TimerUDB:sT8:timerdp:u0\/clock \Timer:TimerUDB:sT8:timerdp:u0\/z0_comb 3.270
Route 1 \Timer:TimerUDB:per_zero\ \Timer:TimerUDB:sT8:timerdp:u0\/z0_comb \Timer:TimerUDB:status_tc\/main_1 4.108
macrocell9 U(1,3) 1 \Timer:TimerUDB:status_tc\ \Timer:TimerUDB:status_tc\/main_1 \Timer:TimerUDB:status_tc\/q 3.350
Route 1 \Timer:TimerUDB:status_tc\ \Timer:TimerUDB:status_tc\/q \Timer:TimerUDB:rstSts:stsreg\/status_0 2.311
statusicell3 U(1,3) 1 \Timer:TimerUDB:rstSts:stsreg\ HOLD -2.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Rx_1(0)/fb \UART_ESWIFI:BUART:pollcount_0\/main_2 7.778
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P1[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_620 Rx_1(0)/fb \UART_ESWIFI:BUART:pollcount_0\/main_2 5.038
macrocell23 U(1,2) 1 \UART_ESWIFI:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_ESWIFI:BUART:rx_last\/main_0 7.778
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P1[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_620 Rx_1(0)/fb \UART_ESWIFI:BUART:rx_last\/main_0 5.038
macrocell25 U(1,2) 1 \UART_ESWIFI:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_ESWIFI:BUART:pollcount_1\/main_3 8.559
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P1[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_620 Rx_1(0)/fb \UART_ESWIFI:BUART:pollcount_1\/main_3 5.819
macrocell22 U(1,3) 1 \UART_ESWIFI:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_ESWIFI:BUART:rx_state_2\/main_8 8.706
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P1[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_620 Rx_1(0)/fb \UART_ESWIFI:BUART:rx_state_2\/main_8 5.966
macrocell19 U(1,1) 1 \UART_ESWIFI:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_ESWIFI:BUART:rx_status_3\/main_6 8.706
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P1[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_620 Rx_1(0)/fb \UART_ESWIFI:BUART:rx_status_3\/main_6 5.966
macrocell24 U(1,1) 1 \UART_ESWIFI:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_ESWIFI:BUART:rx_state_0\/main_9 8.719
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P1[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_620 Rx_1(0)/fb \UART_ESWIFI:BUART:rx_state_0\/main_9 5.979
macrocell16 U(1,1) 1 \UART_ESWIFI:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_ESWIFI:BUART:sRX:RxShifter:u0\/route_si 13.417
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P1[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_620 Rx_1(0)/fb \UART_ESWIFI:BUART:rx_postpoll\/main_1 5.038
macrocell6 U(1,2) 1 \UART_ESWIFI:BUART:rx_postpoll\ \UART_ESWIFI:BUART:rx_postpoll\/main_1 \UART_ESWIFI:BUART:rx_postpoll\/q 3.350
Route 1 \UART_ESWIFI:BUART:rx_postpoll\ \UART_ESWIFI:BUART:rx_postpoll\/q \UART_ESWIFI:BUART:sRX:RxShifter:u0\/route_si 2.289
datapathcell3 U(1,2) 1 \UART_ESWIFI:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART_ESWIFI:BUART:rx_status_3\/q \UART_ESWIFI:BUART:sRX:RxSts\/status_3 2.180
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(1,1) 1 \UART_ESWIFI:BUART:rx_status_3\ \UART_ESWIFI:BUART:rx_status_3\/clock_0 \UART_ESWIFI:BUART:rx_status_3\/q 1.250
Route 1 \UART_ESWIFI:BUART:rx_status_3\ \UART_ESWIFI:BUART:rx_status_3\/q \UART_ESWIFI:BUART:sRX:RxSts\/status_3 2.930
statusicell2 U(1,2) 1 \UART_ESWIFI:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART_ESWIFI:BUART:rx_state_3\/q \UART_ESWIFI:BUART:rx_state_3\/main_3 3.542
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(1,2) 1 \UART_ESWIFI:BUART:rx_state_3\ \UART_ESWIFI:BUART:rx_state_3\/clock_0 \UART_ESWIFI:BUART:rx_state_3\/q 1.250
macrocell18 U(1,2) 1 \UART_ESWIFI:BUART:rx_state_3\ \UART_ESWIFI:BUART:rx_state_3\/q \UART_ESWIFI:BUART:rx_state_3\/main_3 2.292
macrocell18 U(1,2) 1 \UART_ESWIFI:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
\UART_ESWIFI:BUART:rx_state_3\/q \UART_ESWIFI:BUART:rx_state_stop1_reg\/main_2 3.542
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(1,2) 1 \UART_ESWIFI:BUART:rx_state_3\ \UART_ESWIFI:BUART:rx_state_3\/clock_0 \UART_ESWIFI:BUART:rx_state_3\/q 1.250
Route 1 \UART_ESWIFI:BUART:rx_state_3\ \UART_ESWIFI:BUART:rx_state_3\/q \UART_ESWIFI:BUART:rx_state_stop1_reg\/main_2 2.292
macrocell21 U(1,2) 1 \UART_ESWIFI:BUART:rx_state_stop1_reg\ HOLD 0.000
Clock Skew 0.000
\UART_ESWIFI:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_ESWIFI:BUART:tx_state_2\/main_4 3.662
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,2) 1 \UART_ESWIFI:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_ESWIFI:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_ESWIFI:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 1.000
Route 1 \UART_ESWIFI:BUART:tx_counter_dp\ \UART_ESWIFI:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_ESWIFI:BUART:tx_state_2\/main_4 2.662
macrocell13 U(0,2) 1 \UART_ESWIFI:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_ESWIFI:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_ESWIFI:BUART:tx_state_2\/main_2 3.786
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,2) 1 \UART_ESWIFI:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_ESWIFI:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_ESWIFI:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 1.000
Route 1 \UART_ESWIFI:BUART:tx_bitclk_enable_pre\ \UART_ESWIFI:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_ESWIFI:BUART:tx_state_2\/main_2 2.786
macrocell13 U(0,2) 1 \UART_ESWIFI:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_ESWIFI:BUART:rx_state_2\/q \UART_ESWIFI:BUART:rx_state_0\/main_4 3.830
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(1,1) 1 \UART_ESWIFI:BUART:rx_state_2\ \UART_ESWIFI:BUART:rx_state_2\/clock_0 \UART_ESWIFI:BUART:rx_state_2\/q 1.250
Route 1 \UART_ESWIFI:BUART:rx_state_2\ \UART_ESWIFI:BUART:rx_state_2\/q \UART_ESWIFI:BUART:rx_state_0\/main_4 2.580
macrocell16 U(1,1) 1 \UART_ESWIFI:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_ESWIFI:BUART:rx_state_2\/q \UART_ESWIFI:BUART:rx_load_fifo\/main_4 3.831
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(1,1) 1 \UART_ESWIFI:BUART:rx_state_2\ \UART_ESWIFI:BUART:rx_state_2\/clock_0 \UART_ESWIFI:BUART:rx_state_2\/q 1.250
Route 1 \UART_ESWIFI:BUART:rx_state_2\ \UART_ESWIFI:BUART:rx_state_2\/q \UART_ESWIFI:BUART:rx_load_fifo\/main_4 2.581
macrocell17 U(1,1) 1 \UART_ESWIFI:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART_ESWIFI:BUART:rx_state_2\/q \UART_ESWIFI:BUART:rx_state_2\/main_4 3.831
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(1,1) 1 \UART_ESWIFI:BUART:rx_state_2\ \UART_ESWIFI:BUART:rx_state_2\/clock_0 \UART_ESWIFI:BUART:rx_state_2\/q 1.250
macrocell19 U(1,1) 1 \UART_ESWIFI:BUART:rx_state_2\ \UART_ESWIFI:BUART:rx_state_2\/q \UART_ESWIFI:BUART:rx_state_2\/main_4 2.581
macrocell19 U(1,1) 1 \UART_ESWIFI:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_ESWIFI:BUART:rx_state_2\/q \UART_ESWIFI:BUART:rx_status_3\/main_4 3.831
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(1,1) 1 \UART_ESWIFI:BUART:rx_state_2\ \UART_ESWIFI:BUART:rx_state_2\/clock_0 \UART_ESWIFI:BUART:rx_state_2\/q 1.250
Route 1 \UART_ESWIFI:BUART:rx_state_2\ \UART_ESWIFI:BUART:rx_state_2\/q \UART_ESWIFI:BUART:rx_status_3\/main_4 2.581
macrocell24 U(1,1) 1 \UART_ESWIFI:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
\UART_ESWIFI:BUART:pollcount_1\/q \UART_ESWIFI:BUART:pollcount_1\/main_2 3.868
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(1,3) 1 \UART_ESWIFI:BUART:pollcount_1\ \UART_ESWIFI:BUART:pollcount_1\/clock_0 \UART_ESWIFI:BUART:pollcount_1\/q 1.250
macrocell22 U(1,3) 1 \UART_ESWIFI:BUART:pollcount_1\ \UART_ESWIFI:BUART:pollcount_1\/q \UART_ESWIFI:BUART:pollcount_1\/main_2 2.618
macrocell22 U(1,3) 1 \UART_ESWIFI:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ Clock_PWM(FFB)
Source Destination Delay (ns)
\PWM_Green:cy_m0s8_tcpwm_1\/line_out Pin_GreenLED(0)_PAD 18.011
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8tcpwmcell F(TCPWM,0) 1 \PWM_Green:cy_m0s8_tcpwm_1\ \PWM_Green:cy_m0s8_tcpwm_1\/clock \PWM_Green:cy_m0s8_tcpwm_1\/line_out 0.000
Route 1 Net_1207 \PWM_Green:cy_m0s8_tcpwm_1\/line_out Pin_GreenLED(0)/pin_input 3.781
iocell1 P5[3] 1 Pin_GreenLED(0) Pin_GreenLED(0)/pin_input Pin_GreenLED(0)/pad_out 14.230
Route 1 Pin_GreenLED(0)_PAD Pin_GreenLED(0)/pad_out Pin_GreenLED(0)_PAD 0.000
Clock Clock path delay 0.000
\PWM_Red:cy_m0s8_tcpwm_1\/line_out Pin_RedLED(0)_PAD 17.700
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8tcpwmcell F(TCPWM,2) 1 \PWM_Red:cy_m0s8_tcpwm_1\ \PWM_Red:cy_m0s8_tcpwm_1\/clock \PWM_Red:cy_m0s8_tcpwm_1\/line_out 0.000
Route 1 Net_1144 \PWM_Red:cy_m0s8_tcpwm_1\/line_out Pin_RedLED(0)/pin_input 3.750
iocell2 P5[2] 1 Pin_RedLED(0) Pin_RedLED(0)/pin_input Pin_RedLED(0)/pad_out 13.950
Route 1 Pin_RedLED(0)_PAD Pin_RedLED(0)/pad_out Pin_RedLED(0)_PAD 0.000
Clock Clock path delay 0.000
\PWM_Blue:cy_m0s8_tcpwm_1\/line_out Pin_BlueLED(0)_PAD 17.605
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8tcpwmcell F(TCPWM,1) 1 \PWM_Blue:cy_m0s8_tcpwm_1\ \PWM_Blue:cy_m0s8_tcpwm_1\/clock \PWM_Blue:cy_m0s8_tcpwm_1\/line_out 0.000
Route 1 Net_1239 \PWM_Blue:cy_m0s8_tcpwm_1\/line_out Pin_BlueLED(0)/pin_input 3.755
iocell3 P5[4] 1 Pin_BlueLED(0) Pin_BlueLED(0)/pin_input Pin_BlueLED(0)/pad_out 13.850
Route 1 Pin_BlueLED(0)_PAD Pin_BlueLED(0)/pad_out Pin_BlueLED(0)_PAD 0.000
Clock Clock path delay 0.000
+ UART_ESWIFI_IntClock
Source Destination Delay (ns)
\UART_ESWIFI:BUART:txn\/q Tx_1(0)_PAD 28.252
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(0,3) 1 \UART_ESWIFI:BUART:txn\ \UART_ESWIFI:BUART:txn\/clock_0 \UART_ESWIFI:BUART:txn\/q 1.250
Route 1 \UART_ESWIFI:BUART:txn\ \UART_ESWIFI:BUART:txn\/q Net_615/main_0 2.802
macrocell1 U(1,3) 1 Net_615 Net_615/main_0 Net_615/q 3.350
Route 1 Net_615 Net_615/q Tx_1(0)/pin_input 5.530
iocell8 P0[2] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 15.320
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000