Static Timing Analysis

Project : Design01
Build Time : 04/23/13 14:37:36
Device : CY8C3866AXI-040
Temperature : -40C - 85/125C
Vdda : 5.00
Vddd : 5.00
Vio0 : 5.00
Vio1 : 5.00
Vio2 : 5.00
Vio3 : 5.00
Voltage : 5.0
Vusb : 5.00
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_Ext_CP_Clk(routed) ADC_Ext_CP_Clk(routed) 12.000 MHz 12.000 MHz N/A
ADC_theACLK(fixed-function) ADC_theACLK(fixed-function) 3.000 MHz 3.000 MHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
ADC_Ext_CP_Clk CyMASTER_CLK 12.000 MHz 12.000 MHz N/A
ADC_theACLK CyMASTER_CLK 3.000 MHz 3.000 MHz N/A
UART_1_IntClock CyMASTER_CLK 923.077 kHz 923.077 kHz 40.803 MHz
timer_clock CyMASTER_CLK 1.000 kHz 1.000 kHz 43.142 MHz
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 44.236 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
tmp__cydff_2_reg/q \Tick_Event:sts_reg\/status_0 92.739 MHz 10.783 30.884
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell30 U(2,5) 1 tmp__cydff_2_reg tmp__cydff_2_reg/clock_0 tmp__cydff_2_reg/q 1.250
Route 1 tmp__cydff_2_reg tmp__cydff_2_reg/q Net_127/main_0 2.288
macrocell1 U(2,5) 1 Net_127 Net_127/main_0 Net_127/q 3.350
Route 1 Net_127 Net_127/q \Tick_Event:sts_reg\/status_0 2.325
statuscell1 U(2,5) 1 \Tick_Event:sts_reg\ SETUP 1.570
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 44.236 MHz 22.606 19.061
Type Location Fanout Instance/Net Source Dest Delay (ns)
sio_ireg P12[2] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 6.160
Route 1 Net_7 Rx(0)/fb \UART_1:BUART:rx_postpoll\/main_1 5.597
macrocell13 U(3,3) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.289
datapathcell3 U(3,3) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
Rx(0)/fb \UART_1:BUART:rx_state_0\/main_9 61.099 MHz 16.367 25.300
Type Location Fanout Instance/Net Source Dest Delay (ns)
sio_ireg P12[2] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 6.160
Route 1 Net_7 Rx(0)/fb \UART_1:BUART:rx_state_0\/main_9 6.697
macrocell14 U(3,2) 1 \UART_1:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx(0)/fb \UART_1:BUART:pollcount_1\/main_3 61.136 MHz 16.357 25.310
Type Location Fanout Instance/Net Source Dest Delay (ns)
sio_ireg P12[2] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 6.160
Route 1 Net_7 Rx(0)/fb \UART_1:BUART:pollcount_1\/main_3 6.687
macrocell7 U(3,2) 1 \UART_1:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx(0)/fb \UART_1:BUART:rx_last\/main_0 62.282 MHz 16.056 25.611
Type Location Fanout Instance/Net Source Dest Delay (ns)
sio_ireg P12[2] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 6.160
Route 1 Net_7 Rx(0)/fb \UART_1:BUART:rx_last\/main_0 6.386
macrocell11 U(3,4) 1 \UART_1:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Rx(0)/fb \UART_1:BUART:rx_state_2\/main_8 62.282 MHz 16.056 25.611
Type Location Fanout Instance/Net Source Dest Delay (ns)
sio_ireg P12[2] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 6.160
Route 1 Net_7 Rx(0)/fb \UART_1:BUART:rx_state_2\/main_8 6.386
macrocell15 U(3,4) 1 \UART_1:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx(0)/fb \UART_1:BUART:pollcount_0\/main_2 65.436 MHz 15.282 26.385
Type Location Fanout Instance/Net Source Dest Delay (ns)
sio_ireg P12[2] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 6.160
Route 1 Net_7 Rx(0)/fb \UART_1:BUART:pollcount_0\/main_2 5.612
macrocell6 U(3,3) 1 \UART_1:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Rx(0)/fb \UART_1:BUART:rx_status_3\/main_6 65.436 MHz 15.282 26.385
Type Location Fanout Instance/Net Source Dest Delay (ns)
sio_ireg P12[2] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 6.160
Route 1 Net_7 Rx(0)/fb \UART_1:BUART:rx_status_3\/main_6 5.612
macrocell18 U(3,3) 1 \UART_1:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 1083.33ns(923.077 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 40.803 MHz 24.508 1058.825
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(2,3) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:counter_load_not\/main_2 6.075
macrocell5 U(2,5) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_2 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.313
datapathcell5 U(2,5) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 43.668 MHz 22.900 1060.433
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(2,4) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:counter_load_not\/main_0 4.467
macrocell5 U(2,5) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_0 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.313
datapathcell5 U(2,5) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:tx_bitclk\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 45.660 MHz 21.901 1061.432
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(3,5) 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/clock_0 \UART_1:BUART:tx_bitclk\/q 1.250
Route 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/q \UART_1:BUART:counter_load_not\/main_3 3.468
macrocell5 U(2,5) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_3 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.313
datapathcell5 U(2,5) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 45.838 MHz 21.816 1061.517
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(3,5) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:counter_load_not\/main_1 3.383
macrocell5 U(2,5) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_1 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.313
datapathcell5 U(2,5) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 47.099 MHz 21.232 1062.101
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(2,5) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb 5.680
Route 1 \UART_1:BUART:tx_bitclk_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_1:BUART:tx_bitclk_enable_pre\/main_0 3.613
macrocell22 U(3,5) 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:tx_bitclk_enable_pre\/main_0 \UART_1:BUART:tx_bitclk_enable_pre\/q 3.350
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:tx_bitclk_enable_pre\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 2.299
datapathcell4 U(3,5) 1 \UART_1:BUART:sTX:TxShifter:u0\ SETUP 6.290
Clock Skew 0.000
\UART_1:BUART:rx_state_2\/q \UART_1:BUART:sRX:RxBitCounter\/load 49.895 MHz 20.042 1063.291
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(3,4) 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/clock_0 \UART_1:BUART:rx_state_2\/q 1.250
Route 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/q \UART_1:BUART:rx_counter_load\/main_3 8.906
macrocell10 U(2,2) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_3 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.316
count7cell U(2,2) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 4.220
Clock Skew 0.000
\UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:sRX:RxSts\/status_4 55.285 MHz 18.088 1065.245
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(3,3) 1 \UART_1:BUART:sRX:RxShifter:u0\ \UART_1:BUART:sRX:RxShifter:u0\/clock \UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART_1:BUART:rx_fifofull\ \UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:rx_status_4\/main_1 2.324
macrocell19 U(3,3) 1 \UART_1:BUART:rx_status_4\ \UART_1:BUART:rx_status_4\/main_1 \UART_1:BUART:rx_status_4\/q 3.350
Route 1 \UART_1:BUART:rx_status_4\ \UART_1:BUART:rx_status_4\/q \UART_1:BUART:sRX:RxSts\/status_4 5.564
statusicell2 U(3,3) 1 \UART_1:BUART:sRX:RxSts\ SETUP 1.570
Clock Skew 0.000
\UART_1:BUART:rx_state_3\/q \UART_1:BUART:sRX:RxBitCounter\/load 55.630 MHz 17.976 1065.357
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(3,4) 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/clock_0 \UART_1:BUART:rx_state_3\/q 1.250
Route 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/q \UART_1:BUART:rx_counter_load\/main_2 6.840
macrocell10 U(2,2) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_2 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.316
count7cell U(2,2) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 4.220
Clock Skew 0.000
\UART_1:BUART:rx_state_2\/q \UART_1:BUART:rx_state_stop1_reg\/main_3 59.119 MHz 16.915 1066.418
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(3,4) 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/clock_0 \UART_1:BUART:rx_state_2\/q 1.250
Route 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/q \UART_1:BUART:rx_state_stop1_reg\/main_3 12.155
macrocell17 U(3,2) 1 \UART_1:BUART:rx_state_stop1_reg\ SETUP 3.510
Clock Skew 0.000
\UART_1:BUART:rx_state_2\/q \UART_1:BUART:rx_state_0\/main_4 59.196 MHz 16.893 1066.440
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(3,4) 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/clock_0 \UART_1:BUART:rx_state_2\/q 1.250
Route 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/q \UART_1:BUART:rx_state_0\/main_4 12.133
macrocell14 U(3,2) 1 \UART_1:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Net_144/q \Tick_Event:sts_reg\/status_0 92.644 MHz 10.794 30.873
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(2,5) 1 Net_144 Net_144/clock_0 Net_144/q 1.250
Route 1 Net_144 Net_144/q Net_127/main_1 2.299
macrocell1 U(2,5) 1 Net_127 Net_127/main_1 Net_127/q 3.350
Route 1 Net_127 Net_127/q \Tick_Event:sts_reg\/status_0 2.325
statuscell1 U(2,5) 1 \Tick_Event:sts_reg\ SETUP 1.570
Clock Skew 0.000
Net_144/q tmp__cydff_2_reg/main_0 141.663 MHz 7.059 34.608
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(2,5) 1 Net_144 Net_144/clock_0 Net_144/q 1.250
Route 1 Net_144 Net_144/q tmp__cydff_2_reg/main_0 2.299
macrocell30 U(2,5) 1 tmp__cydff_2_reg SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 1e+006ns(1 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Tick_Timer:TimerUDB:sT16:timerdp:u0\/z0 \Tick_Timer:TimerUDB:sT16:timerdp:u1\/ci 43.142 MHz 23.179 999976.821
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u0\ \Tick_Timer:TimerUDB:sT16:timerdp:u0\/clock \Tick_Timer:TimerUDB:sT16:timerdp:u0\/z0 2.320
Route 1 \Tick_Timer:TimerUDB:sT16:timerdp:u0.z0__sig\ \Tick_Timer:TimerUDB:sT16:timerdp:u0\/z0 \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell2 U(2,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u1\ \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0i \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0_comb 2.960
Route 1 \Tick_Timer:TimerUDB:per_zero\ \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Tick_Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.099
datapathcell1 U(3,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u0\ \Tick_Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_0 \Tick_Timer:TimerUDB:sT16:timerdp:u0\/co_msb 9.710
Route 1 \Tick_Timer:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Tick_Timer:TimerUDB:sT16:timerdp:u0\/co_msb \Tick_Timer:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell2 U(2,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
\Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Tick_Timer:TimerUDB:sT16:timerdp:u1\/ci 45.979 MHz 21.749 999978.251
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u1\ \Tick_Timer:TimerUDB:sT16:timerdp:u1\/clock \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0_comb 3.850
Route 1 \Tick_Timer:TimerUDB:per_zero\ \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Tick_Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.099
datapathcell1 U(3,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u0\ \Tick_Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_0 \Tick_Timer:TimerUDB:sT16:timerdp:u0\/co_msb 9.710
Route 1 \Tick_Timer:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Tick_Timer:TimerUDB:sT16:timerdp:u0\/co_msb \Tick_Timer:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell2 U(2,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
\Tick_Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Tick_Timer:TimerUDB:sT16:timerdp:u1\/ci 46.847 MHz 21.346 999978.654
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,4) 1 \Tick_Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Tick_Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Tick_Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \Tick_Timer:TimerUDB:control_7\ \Tick_Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Tick_Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_1 3.966
datapathcell1 U(3,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u0\ \Tick_Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_1 \Tick_Timer:TimerUDB:sT16:timerdp:u0\/co_msb 9.710
Route 1 \Tick_Timer:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Tick_Timer:TimerUDB:sT16:timerdp:u0\/co_msb \Tick_Timer:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell2 U(2,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
\Tick_Timer:TimerUDB:sT16:timerdp:u0\/z0 \Tick_Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_0 50.254 MHz 19.899 999980.101
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u0\ \Tick_Timer:TimerUDB:sT16:timerdp:u0\/clock \Tick_Timer:TimerUDB:sT16:timerdp:u0\/z0 2.320
Route 1 \Tick_Timer:TimerUDB:sT16:timerdp:u0.z0__sig\ \Tick_Timer:TimerUDB:sT16:timerdp:u0\/z0 \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell2 U(2,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u1\ \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0i \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0_comb 2.960
Route 1 \Tick_Timer:TimerUDB:per_zero\ \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Tick_Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.099
datapathcell1 U(3,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u0\ SETUP 11.520
Clock Skew 0.000
\Tick_Timer:TimerUDB:sT16:timerdp:u0\/z0 \Tick_Timer:TimerUDB:sT16:timerdp:u1\/cs_addr_0 50.569 MHz 19.775 999980.225
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u0\ \Tick_Timer:TimerUDB:sT16:timerdp:u0\/clock \Tick_Timer:TimerUDB:sT16:timerdp:u0\/z0 2.320
Route 1 \Tick_Timer:TimerUDB:sT16:timerdp:u0.z0__sig\ \Tick_Timer:TimerUDB:sT16:timerdp:u0\/z0 \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell2 U(2,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u1\ \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0i \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0_comb 2.960
datapathcell2 U(2,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u1\ \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Tick_Timer:TimerUDB:sT16:timerdp:u1\/cs_addr_0 2.975
datapathcell2 U(2,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u1\ SETUP 11.520
Clock Skew 0.000
\Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Tick_Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_0 54.145 MHz 18.469 999981.531
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u1\ \Tick_Timer:TimerUDB:sT16:timerdp:u1\/clock \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0_comb 3.850
Route 1 \Tick_Timer:TimerUDB:per_zero\ \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Tick_Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.099
datapathcell1 U(3,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u0\ SETUP 11.520
Clock Skew 0.000
\Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Tick_Timer:TimerUDB:sT16:timerdp:u1\/cs_addr_0 54.511 MHz 18.345 999981.655
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u1\ \Tick_Timer:TimerUDB:sT16:timerdp:u1\/clock \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0_comb 3.850
datapathcell2 U(2,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u1\ \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Tick_Timer:TimerUDB:sT16:timerdp:u1\/cs_addr_0 2.975
datapathcell2 U(2,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u1\ SETUP 11.520
Clock Skew 0.000
\Tick_Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Tick_Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_1 55.353 MHz 18.066 999981.934
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,4) 1 \Tick_Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Tick_Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Tick_Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \Tick_Timer:TimerUDB:control_7\ \Tick_Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Tick_Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_1 3.966
datapathcell1 U(3,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u0\ SETUP 11.520
Clock Skew 0.000
\Tick_Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Tick_Timer:TimerUDB:sT16:timerdp:u1\/cs_addr_1 56.625 MHz 17.660 999982.340
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,4) 1 \Tick_Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Tick_Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Tick_Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \Tick_Timer:TimerUDB:control_7\ \Tick_Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Tick_Timer:TimerUDB:sT16:timerdp:u1\/cs_addr_1 3.560
datapathcell2 U(2,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u1\ SETUP 11.520
Clock Skew 0.000
\Tick_Timer:TimerUDB:sT16:timerdp:u0\/z0 \Tick_Timer:TimerUDB:rstSts:stsreg\/status_0 63.943 MHz 15.639 999984.361
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u0\ \Tick_Timer:TimerUDB:sT16:timerdp:u0\/clock \Tick_Timer:TimerUDB:sT16:timerdp:u0\/z0 2.320
Route 1 \Tick_Timer:TimerUDB:sT16:timerdp:u0.z0__sig\ \Tick_Timer:TimerUDB:sT16:timerdp:u0\/z0 \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell2 U(2,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u1\ \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0i \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0_comb 2.960
Route 1 \Tick_Timer:TimerUDB:per_zero\ \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Tick_Timer:TimerUDB:status_tc\/main_1 3.109
macrocell4 U(2,4) 1 \Tick_Timer:TimerUDB:status_tc\ \Tick_Timer:TimerUDB:status_tc\/main_1 \Tick_Timer:TimerUDB:status_tc\/q 3.350
Route 1 \Tick_Timer:TimerUDB:status_tc\ \Tick_Timer:TimerUDB:status_tc\/q \Tick_Timer:TimerUDB:rstSts:stsreg\/status_0 2.330
statusicell1 U(2,4) 1 \Tick_Timer:TimerUDB:rstSts:stsreg\ SETUP 1.570
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
tmp__cydff_2_reg/q \Tick_Event:sts_reg\/status_0 7.213
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell30 U(2,5) 1 tmp__cydff_2_reg tmp__cydff_2_reg/clock_0 tmp__cydff_2_reg/q 1.250
Route 1 tmp__cydff_2_reg tmp__cydff_2_reg/q Net_127/main_0 2.288
macrocell1 U(2,5) 1 Net_127 Net_127/main_0 Net_127/q 3.350
Route 1 Net_127 Net_127/q \Tick_Event:sts_reg\/status_0 2.325
statuscell1 U(2,5) 1 \Tick_Event:sts_reg\ HOLD -2.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Rx(0)/fb \UART_1:BUART:pollcount_0\/main_2 11.772
Type Location Fanout Instance/Net Source Dest Delay (ns)
sio_ireg P12[2] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 6.160
Route 1 Net_7 Rx(0)/fb \UART_1:BUART:pollcount_0\/main_2 5.612
macrocell6 U(3,3) 1 \UART_1:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx(0)/fb \UART_1:BUART:rx_status_3\/main_6 11.772
Type Location Fanout Instance/Net Source Dest Delay (ns)
sio_ireg P12[2] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 6.160
Route 1 Net_7 Rx(0)/fb \UART_1:BUART:rx_status_3\/main_6 5.612
macrocell18 U(3,3) 1 \UART_1:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx(0)/fb \UART_1:BUART:rx_last\/main_0 12.546
Type Location Fanout Instance/Net Source Dest Delay (ns)
sio_ireg P12[2] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 6.160
Route 1 Net_7 Rx(0)/fb \UART_1:BUART:rx_last\/main_0 6.386
macrocell11 U(3,4) 1 \UART_1:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx(0)/fb \UART_1:BUART:rx_state_2\/main_8 12.546
Type Location Fanout Instance/Net Source Dest Delay (ns)
sio_ireg P12[2] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 6.160
Route 1 Net_7 Rx(0)/fb \UART_1:BUART:rx_state_2\/main_8 6.386
macrocell15 U(3,4) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx(0)/fb \UART_1:BUART:pollcount_1\/main_3 12.847
Type Location Fanout Instance/Net Source Dest Delay (ns)
sio_ireg P12[2] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 6.160
Route 1 Net_7 Rx(0)/fb \UART_1:BUART:pollcount_1\/main_3 6.687
macrocell7 U(3,2) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx(0)/fb \UART_1:BUART:rx_state_0\/main_9 12.857
Type Location Fanout Instance/Net Source Dest Delay (ns)
sio_ireg P12[2] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 6.160
Route 1 Net_7 Rx(0)/fb \UART_1:BUART:rx_state_0\/main_9 6.697
macrocell14 U(3,2) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 17.396
Type Location Fanout Instance/Net Source Dest Delay (ns)
sio_ireg P12[2] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 6.160
Route 1 Net_7 Rx(0)/fb \UART_1:BUART:rx_postpoll\/main_1 5.597
macrocell13 U(3,3) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.289
datapathcell3 U(3,3) 1 \UART_1:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 1.567
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(3,3) 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/clock_0 \UART_1:BUART:rx_status_3\/q 1.250
Route 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 2.317
statusicell2 U(3,3) 1 \UART_1:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART_1:BUART:rx_last\/q \UART_1:BUART:rx_state_2\/main_9 3.553
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(3,4) 1 \UART_1:BUART:rx_last\ \UART_1:BUART:rx_last\/clock_0 \UART_1:BUART:rx_last\/q 1.250
Route 1 \UART_1:BUART:rx_last\ \UART_1:BUART:rx_last\/q \UART_1:BUART:rx_state_2\/main_9 2.303
macrocell15 U(3,4) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:rx_bitclk_enable\/q \UART_1:BUART:rx_state_0\/main_2 3.563
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(2,2) 1 \UART_1:BUART:rx_bitclk_enable\ \UART_1:BUART:rx_bitclk_enable\/clock_0 \UART_1:BUART:rx_bitclk_enable\/q 1.250
Route 1 \UART_1:BUART:rx_bitclk_enable\ \UART_1:BUART:rx_bitclk_enable\/q \UART_1:BUART:rx_state_0\/main_2 2.313
macrocell14 U(3,2) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:pollcount_1\/q \UART_1:BUART:pollcount_1\/main_2 3.845
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(3,2) 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/clock_0 \UART_1:BUART:pollcount_1\/q 1.250
macrocell7 U(3,2) 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/q \UART_1:BUART:pollcount_1\/main_2 2.595
macrocell7 U(3,2) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:pollcount_1\/q \UART_1:BUART:rx_state_0\/main_8 3.845
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(3,2) 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/clock_0 \UART_1:BUART:pollcount_1\/q 1.250
Route 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/q \UART_1:BUART:rx_state_0\/main_8 2.595
macrocell14 U(3,2) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:txn\/q \UART_1:BUART:txn\/main_0 3.869
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(2,4) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
macrocell28 U(2,4) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q \UART_1:BUART:txn\/main_0 2.619
macrocell28 U(2,4) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:tx_state_2\/main_2 3.876
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(2,3) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
macrocell25 U(2,3) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:tx_state_2\/main_2 2.626
macrocell25 U(2,3) 1 \UART_1:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:rx_state_3\/q \UART_1:BUART:rx_state_2\/main_3 4.016
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(3,4) 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/clock_0 \UART_1:BUART:rx_state_3\/q 1.250
Route 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/q \UART_1:BUART:rx_state_2\/main_3 2.766
macrocell15 U(3,4) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:txn\/main_1 4.018
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(2,4) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:txn\/main_1 2.768
macrocell28 U(2,4) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:rx_state_3\/q \UART_1:BUART:rx_state_3\/main_3 4.029
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(3,4) 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/clock_0 \UART_1:BUART:rx_state_3\/q 1.250
macrocell16 U(3,4) 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/q \UART_1:BUART:rx_state_3\/main_3 2.779
macrocell16 U(3,4) 1 \UART_1:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Net_144/q tmp__cydff_2_reg/main_0 3.549
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(2,5) 1 Net_144 Net_144/clock_0 Net_144/q 1.250
Route 1 Net_144 Net_144/q tmp__cydff_2_reg/main_0 2.299
macrocell30 U(2,5) 1 tmp__cydff_2_reg HOLD 0.000
Clock Skew 0.000
Net_144/q \Tick_Event:sts_reg\/status_0 7.224
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(2,5) 1 Net_144 Net_144/clock_0 Net_144/q 1.250
Route 1 Net_144 Net_144/q Net_127/main_1 2.299
macrocell1 U(2,5) 1 Net_127 Net_127/main_1 Net_127/q 3.350
Route 1 Net_127 Net_127/q \Tick_Event:sts_reg\/status_0 2.325
statuscell1 U(2,5) 1 \Tick_Event:sts_reg\ HOLD -2.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Tick_Timer:TimerUDB:sT16:timerdp:u0\/co_msb \Tick_Timer:TimerUDB:sT16:timerdp:u1\/ci 3.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u0\ \Tick_Timer:TimerUDB:sT16:timerdp:u0\/clock \Tick_Timer:TimerUDB:sT16:timerdp:u0\/co_msb 3.210
Route 1 \Tick_Timer:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Tick_Timer:TimerUDB:sT16:timerdp:u0\/co_msb \Tick_Timer:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell2 U(2,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Tick_Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Tick_Timer:TimerUDB:sT16:timerdp:u1\/cs_addr_1 5.600
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,4) 1 \Tick_Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Tick_Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Tick_Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.040
Route 1 \Tick_Timer:TimerUDB:control_7\ \Tick_Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Tick_Timer:TimerUDB:sT16:timerdp:u1\/cs_addr_1 3.560
datapathcell2 U(2,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Tick_Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Tick_Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_1 6.006
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,4) 1 \Tick_Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Tick_Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Tick_Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.040
Route 1 \Tick_Timer:TimerUDB:control_7\ \Tick_Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Tick_Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_1 3.966
datapathcell1 U(3,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
\Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Tick_Timer:TimerUDB:sT16:timerdp:u1\/cs_addr_0 6.245
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u1\ \Tick_Timer:TimerUDB:sT16:timerdp:u1\/clock \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0_comb 3.270
datapathcell2 U(2,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u1\ \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Tick_Timer:TimerUDB:sT16:timerdp:u1\/cs_addr_0 2.975
datapathcell2 U(2,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Tick_Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_0 6.369
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u1\ \Tick_Timer:TimerUDB:sT16:timerdp:u1\/clock \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0_comb 3.270
Route 1 \Tick_Timer:TimerUDB:per_zero\ \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Tick_Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.099
datapathcell1 U(3,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
\Tick_Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 Net_144/main_0 6.452
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,4) 1 \Tick_Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Tick_Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Tick_Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.040
Route 1 \Tick_Timer:TimerUDB:control_7\ \Tick_Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 Net_144/main_0 4.412
macrocell2 U(2,5) 1 Net_144 HOLD 0.000
Clock Skew 0.000
\Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0_comb Net_144/main_1 7.276
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u1\ \Tick_Timer:TimerUDB:sT16:timerdp:u1\/clock \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0_comb 3.270
Route 1 \Tick_Timer:TimerUDB:per_zero\ \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0_comb Net_144/main_1 4.006
macrocell2 U(2,5) 1 Net_144 HOLD 0.000
Clock Skew 0.000
\Tick_Timer:TimerUDB:sT16:timerdp:u0\/z0 \Tick_Timer:TimerUDB:sT16:timerdp:u1\/cs_addr_0 7.455
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u0\ \Tick_Timer:TimerUDB:sT16:timerdp:u0\/clock \Tick_Timer:TimerUDB:sT16:timerdp:u0\/z0 1.740
Route 1 \Tick_Timer:TimerUDB:sT16:timerdp:u0.z0__sig\ \Tick_Timer:TimerUDB:sT16:timerdp:u0\/z0 \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell2 U(2,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u1\ \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0i \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0_comb 2.740
datapathcell2 U(2,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u1\ \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Tick_Timer:TimerUDB:sT16:timerdp:u1\/cs_addr_0 2.975
datapathcell2 U(2,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Tick_Timer:TimerUDB:sT16:timerdp:u0\/z0 \Tick_Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_0 7.579
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u0\ \Tick_Timer:TimerUDB:sT16:timerdp:u0\/clock \Tick_Timer:TimerUDB:sT16:timerdp:u0\/z0 1.740
Route 1 \Tick_Timer:TimerUDB:sT16:timerdp:u0.z0__sig\ \Tick_Timer:TimerUDB:sT16:timerdp:u0\/z0 \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell2 U(2,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u1\ \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0i \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0_comb 2.740
Route 1 \Tick_Timer:TimerUDB:per_zero\ \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Tick_Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.099
datapathcell1 U(3,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
\Tick_Timer:TimerUDB:sT16:timerdp:u0\/z0 Net_144/main_1 8.486
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u0\ \Tick_Timer:TimerUDB:sT16:timerdp:u0\/clock \Tick_Timer:TimerUDB:sT16:timerdp:u0\/z0 1.740
Route 1 \Tick_Timer:TimerUDB:sT16:timerdp:u0.z0__sig\ \Tick_Timer:TimerUDB:sT16:timerdp:u0\/z0 \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell2 U(2,4) 1 \Tick_Timer:TimerUDB:sT16:timerdp:u1\ \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0i \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0_comb 2.740
Route 1 \Tick_Timer:TimerUDB:per_zero\ \Tick_Timer:TimerUDB:sT16:timerdp:u1\/z0_comb Net_144/main_1 4.006
macrocell2 U(2,5) 1 Net_144 HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
Rx(0)/fb RX_Debug(0)_PAD 32.030
Type Location Fanout Instance/Net Source Dest Delay (ns)
sio_ireg P12[2] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 6.160
Route 1 Net_7 Rx(0)/fb RX_Debug(0)/pin_input 9.670
iocell P6[0] 1 RX_Debug(0) RX_Debug(0)/pin_input RX_Debug(0)/pad_out 16.200
Route 1 RX_Debug(0)_PAD RX_Debug(0)/pad_out RX_Debug(0)_PAD 0.000
Clock Clock path delay 0.000
+ UART_1_IntClock
Source Destination Delay (ns)
\UART_1:BUART:txn\/q TX_Debug(0)_PAD 32.412
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(2,4) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
Route 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q Net_2/main_0 3.411
macrocell3 U(2,3) 1 Net_2 Net_2/main_0 Net_2/q 3.350
Route 1 Net_2 Net_2/q TX_Debug(0)/pin_input 8.201
iocell P6[6] 1 TX_Debug(0) TX_Debug(0)/pin_input TX_Debug(0)/pad_out 16.200
Route 1 TX_Debug(0)_PAD TX_Debug(0)/pad_out TX_Debug(0)_PAD 0.000
Clock Clock path delay 0.000
\UART_1:BUART:txn\/q Tx(0)_PAD 31.368
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(2,4) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
Route 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q Net_2/main_0 3.411
macrocell3 U(2,3) 1 Net_2 Net_2/main_0 Net_2/q 3.350
Route 1 Net_2 Net_2/q Tx(0)/pin_input 6.357
sio P12[3] 1 Tx(0) Tx(0)/pin_input Tx(0)/pad_out 17.000
Route 1 Tx(0)_PAD Tx(0)/pad_out Tx(0)_PAD 0.000
Clock Clock path delay 0.000