Static Timing Analysis

Project : USB_UART01
Build Time : 02/27/13 13:42:58
Device : CY8C3866AXI-040
Temperature : -40C - 85/125C
Vdda : 3.30
Vddd : 3.30
Vio0 : 3.30
Vio1 : 3.30
Vio2 : 3.30
Vio3 : 3.30
Voltage : 3.3
Vusb : 3.30
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 100.000 kHz 100.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
UART_1_IntClock CyMASTER_CLK 923.077 kHz 923.077 kHz 35.273 MHz
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 41.149 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 41.149 MHz 24.302 17.365
Type Location Fanout Instance/Net Source Dest Delay (ns)
sio_ireg P12[2] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 6.160
Route 1 Net_7 Rx(0)/fb \UART_1:BUART:rx_postpoll\/main_1 7.273
macrocell10 U(3,5) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.309
datapathcell1 U(3,5) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
Rx(0)/fb \UART_1:BUART:rx_state_2\/main_8 64.876 MHz 15.414 26.253
Type Location Fanout Instance/Net Source Dest Delay (ns)
sio_ireg P12[2] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 6.160
Route 1 Net_7 Rx(0)/fb \UART_1:BUART:rx_state_2\/main_8 5.744
macrocell12 U(3,4) 1 \UART_1:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx(0)/fb \UART_1:BUART:rx_state_0\/main_9 64.960 MHz 15.394 26.273
Type Location Fanout Instance/Net Source Dest Delay (ns)
sio_ireg P12[2] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 6.160
Route 1 Net_7 Rx(0)/fb \UART_1:BUART:rx_state_0\/main_9 5.724
macrocell11 U(3,4) 1 \UART_1:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx(0)/fb \UART_1:BUART:pollcount_0\/main_2 69.813 MHz 14.324 27.343
Type Location Fanout Instance/Net Source Dest Delay (ns)
sio_ireg P12[2] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 6.160
Route 1 Net_7 Rx(0)/fb \UART_1:BUART:pollcount_0\/main_2 4.654
macrocell3 U(3,3) 1 \UART_1:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Rx(0)/fb \UART_1:BUART:pollcount_1\/main_3 69.813 MHz 14.324 27.343
Type Location Fanout Instance/Net Source Dest Delay (ns)
sio_ireg P12[2] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 6.160
Route 1 Net_7 Rx(0)/fb \UART_1:BUART:pollcount_1\/main_3 4.654
macrocell4 U(3,3) 1 \UART_1:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx(0)/fb \UART_1:BUART:rx_last\/main_0 69.813 MHz 14.324 27.343
Type Location Fanout Instance/Net Source Dest Delay (ns)
sio_ireg P12[2] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 6.160
Route 1 Net_7 Rx(0)/fb \UART_1:BUART:rx_last\/main_0 4.654
macrocell8 U(3,3) 1 \UART_1:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Rx(0)/fb \UART_1:BUART:rx_status_3\/main_6 69.813 MHz 14.324 27.343
Type Location Fanout Instance/Net Source Dest Delay (ns)
sio_ireg P12[2] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 6.160
Route 1 Net_7 Rx(0)/fb \UART_1:BUART:rx_status_3\/main_6 4.654
macrocell15 U(3,3) 1 \UART_1:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 1083.33ns(923.077 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_1:BUART:tx_bitclk\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 35.273 MHz 28.350 1054.983
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(2,3) 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/clock_0 \UART_1:BUART:tx_bitclk\/q 1.250
Route 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/q \UART_1:BUART:counter_load_not\/main_3 8.569
macrocell2 U(3,5) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_3 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 3.661
datapathcell3 U(2,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 37.533 MHz 26.643 1056.690
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(2,3) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:counter_load_not\/main_1 6.862
macrocell2 U(3,5) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_1 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 3.661
datapathcell3 U(2,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 38.842 MHz 25.745 1057.588
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(2,3) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:counter_load_not\/main_0 5.964
macrocell2 U(3,5) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_0 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 3.661
datapathcell3 U(2,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 42.130 MHz 23.736 1059.597
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(2,5) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:counter_load_not\/main_2 3.955
macrocell2 U(3,5) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_2 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 3.661
datapathcell3 U(2,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 46.005 MHz 21.737 1061.596
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(2,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb 5.680
Route 1 \UART_1:BUART:tx_bitclk_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_1:BUART:tx_bitclk_enable_pre\/main_0 4.122
macrocell19 U(2,5) 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:tx_bitclk_enable_pre\/main_0 \UART_1:BUART:tx_bitclk_enable_pre\/q 3.350
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:tx_bitclk_enable_pre\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 2.295
datapathcell2 U(2,5) 1 \UART_1:BUART:sTX:TxShifter:u0\ SETUP 6.290
Clock Skew 0.000
\UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:sRX:RxSts\/status_4 56.734 MHz 17.626 1065.707
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,5) 1 \UART_1:BUART:sRX:RxShifter:u0\ \UART_1:BUART:sRX:RxShifter:u0\/clock \UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART_1:BUART:rx_fifofull\ \UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:rx_status_4\/main_1 2.930
macrocell16 U(3,4) 1 \UART_1:BUART:rx_status_4\ \UART_1:BUART:rx_status_4\/main_1 \UART_1:BUART:rx_status_4\/q 3.350
Route 1 \UART_1:BUART:rx_status_4\ \UART_1:BUART:rx_status_4\/q \UART_1:BUART:sRX:RxSts\/status_4 4.496
statusicell1 U(3,3) 1 \UART_1:BUART:sRX:RxSts\ SETUP 1.570
Clock Skew 0.000
\UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:sTX:TxSts\/status_0 59.830 MHz 16.714 1066.619
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,5) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/clock \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART_1:BUART:tx_fifo_empty\ \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:tx_status_0\/main_2 4.191
macrocell23 U(2,4) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_2 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 2.323
statusicell2 U(2,4) 1 \UART_1:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\UART_1:BUART:pollcount_1\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 61.618 MHz 16.229 1067.104
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(3,3) 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/clock_0 \UART_1:BUART:pollcount_1\/q 1.250
Route 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/q \UART_1:BUART:rx_postpoll\/main_0 4.110
macrocell10 U(3,5) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_0 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.309
datapathcell1 U(3,5) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
\UART_1:BUART:pollcount_0\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 61.622 MHz 16.228 1067.105
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(3,3) 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/clock_0 \UART_1:BUART:pollcount_0\/q 1.250
Route 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/q \UART_1:BUART:rx_postpoll\/main_2 4.109
macrocell10 U(3,5) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_2 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.309
datapathcell1 U(3,5) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
\UART_1:BUART:rx_state_2\/q \UART_1:BUART:sRX:RxBitCounter\/load 63.147 MHz 15.836 1067.497
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(3,4) 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/clock_0 \UART_1:BUART:rx_state_2\/q 1.250
Route 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/q \UART_1:BUART:rx_counter_load\/main_3 4.689
macrocell7 U(3,4) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_3 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.327
count7cell U(3,4) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 4.220
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Rx(0)/fb \UART_1:BUART:pollcount_0\/main_2 10.814
Type Location Fanout Instance/Net Source Dest Delay (ns)
sio_ireg P12[2] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 6.160
Route 1 Net_7 Rx(0)/fb \UART_1:BUART:pollcount_0\/main_2 4.654
macrocell3 U(3,3) 1 \UART_1:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx(0)/fb \UART_1:BUART:pollcount_1\/main_3 10.814
Type Location Fanout Instance/Net Source Dest Delay (ns)
sio_ireg P12[2] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 6.160
Route 1 Net_7 Rx(0)/fb \UART_1:BUART:pollcount_1\/main_3 4.654
macrocell4 U(3,3) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx(0)/fb \UART_1:BUART:rx_last\/main_0 10.814
Type Location Fanout Instance/Net Source Dest Delay (ns)
sio_ireg P12[2] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 6.160
Route 1 Net_7 Rx(0)/fb \UART_1:BUART:rx_last\/main_0 4.654
macrocell8 U(3,3) 1 \UART_1:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx(0)/fb \UART_1:BUART:rx_status_3\/main_6 10.814
Type Location Fanout Instance/Net Source Dest Delay (ns)
sio_ireg P12[2] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 6.160
Route 1 Net_7 Rx(0)/fb \UART_1:BUART:rx_status_3\/main_6 4.654
macrocell15 U(3,3) 1 \UART_1:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx(0)/fb \UART_1:BUART:rx_state_0\/main_9 11.884
Type Location Fanout Instance/Net Source Dest Delay (ns)
sio_ireg P12[2] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 6.160
Route 1 Net_7 Rx(0)/fb \UART_1:BUART:rx_state_0\/main_9 5.724
macrocell11 U(3,4) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx(0)/fb \UART_1:BUART:rx_state_2\/main_8 11.904
Type Location Fanout Instance/Net Source Dest Delay (ns)
sio_ireg P12[2] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 6.160
Route 1 Net_7 Rx(0)/fb \UART_1:BUART:rx_state_2\/main_8 5.744
macrocell12 U(3,4) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 19.092
Type Location Fanout Instance/Net Source Dest Delay (ns)
sio_ireg P12[2] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 6.160
Route 1 Net_7 Rx(0)/fb \UART_1:BUART:rx_postpoll\/main_1 7.273
macrocell10 U(3,5) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.309
datapathcell1 U(3,5) 1 \UART_1:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 1.585
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(3,3) 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/clock_0 \UART_1:BUART:rx_status_3\/q 1.250
Route 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 2.335
statusicell1 U(3,3) 1 \UART_1:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART_1:BUART:rx_state_3\/q \UART_1:BUART:rx_state_2\/main_3 3.540
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(3,4) 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/clock_0 \UART_1:BUART:rx_state_3\/q 1.250
Route 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/q \UART_1:BUART:rx_state_2\/main_3 2.290
macrocell12 U(3,4) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:pollcount_0\/q \UART_1:BUART:pollcount_0\/main_3 3.556
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(3,3) 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/clock_0 \UART_1:BUART:pollcount_0\/q 1.250
macrocell3 U(3,3) 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/q \UART_1:BUART:pollcount_0\/main_3 2.306
macrocell3 U(3,3) 1 \UART_1:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:pollcount_0\/q \UART_1:BUART:pollcount_1\/main_4 3.556
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(3,3) 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/clock_0 \UART_1:BUART:pollcount_0\/q 1.250
Route 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/q \UART_1:BUART:pollcount_1\/main_4 2.306
macrocell4 U(3,3) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:pollcount_0\/q \UART_1:BUART:rx_status_3\/main_7 3.556
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(3,3) 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/clock_0 \UART_1:BUART:pollcount_0\/q 1.250
Route 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/q \UART_1:BUART:rx_status_3\/main_7 2.306
macrocell15 U(3,3) 1 \UART_1:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:pollcount_1\/q \UART_1:BUART:pollcount_1\/main_2 3.558
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(3,3) 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/clock_0 \UART_1:BUART:pollcount_1\/q 1.250
macrocell4 U(3,3) 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/q \UART_1:BUART:pollcount_1\/main_2 2.308
macrocell4 U(3,3) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:pollcount_1\/q \UART_1:BUART:rx_status_3\/main_5 3.558
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(3,3) 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/clock_0 \UART_1:BUART:pollcount_1\/q 1.250
Route 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/q \UART_1:BUART:rx_status_3\/main_5 2.308
macrocell15 U(3,3) 1 \UART_1:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:rx_bitclk_enable\/q \UART_1:BUART:rx_status_3\/main_2 3.859
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(3,3) 1 \UART_1:BUART:rx_bitclk_enable\ \UART_1:BUART:rx_bitclk_enable\/clock_0 \UART_1:BUART:rx_bitclk_enable\/q 1.250
Route 1 \UART_1:BUART:rx_bitclk_enable\ \UART_1:BUART:rx_bitclk_enable\/q \UART_1:BUART:rx_status_3\/main_2 2.609
macrocell15 U(3,3) 1 \UART_1:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:tx_state_1\/main_0 3.860
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(2,3) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
macrocell21 U(2,3) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:tx_state_1\/main_0 2.610
macrocell21 U(2,3) 1 \UART_1:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:tx_state_0\/main_0 3.861
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(2,3) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:tx_state_0\/main_0 2.611
macrocell20 U(2,3) 1 \UART_1:BUART:tx_state_0\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
Rx(0)/fb RX_Debug(0)_PAD 33.627
Type Location Fanout Instance/Net Source Dest Delay (ns)
sio_ireg P12[2] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 6.160
Route 1 Net_7 Rx(0)/fb RX_Debug(0)/pin_input 11.267
iocell P6[0] 1 RX_Debug(0) RX_Debug(0)/pin_input RX_Debug(0)/pad_out 16.200
Route 1 RX_Debug(0)_PAD RX_Debug(0)/pad_out RX_Debug(0)_PAD 0.000
Clock Clock path delay 0.000
+ UART_1_IntClock
Source Destination Delay (ns)
\UART_1:BUART:txn\/q Tx(0)_PAD 33.086
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(2,5) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
Route 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q Net_2/main_0 4.173
macrocell1 U(2,5) 1 Net_2 Net_2/main_0 Net_2/q 3.350
Route 1 Net_2 Net_2/q Tx(0)/pin_input 7.313
sio P12[3] 1 Tx(0) Tx(0)/pin_input Tx(0)/pad_out 17.000
Route 1 Tx(0)_PAD Tx(0)/pad_out Tx(0)_PAD 0.000
Clock Clock path delay 0.000
\UART_1:BUART:txn\/q TX_Debug(0)_PAD 32.084
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(2,5) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
Route 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q Net_2/main_0 4.173
macrocell1 U(2,5) 1 Net_2 Net_2/main_0 Net_2/q 3.350
Route 1 Net_2 Net_2/q TX_Debug(0)/pin_input 7.111
iocell P6[6] 1 TX_Debug(0) TX_Debug(0)/pin_input TX_Debug(0)/pad_out 16.200
Route 1 TX_Debug(0)_PAD TX_Debug(0)/pad_out TX_Debug(0)_PAD 0.000
Clock Clock path delay 0.000